View ADAM41P2721_7729351.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

4 - bit single chip microcomputers adam41p272x user`s manual ? adam41p2727 (including i.r. led drive tr.) ? adam41p2723 (including i.r. led drive tr .).) ? ADAM41P2721 (including i.r. led drive tr.) ? adam41p2728 (excluding i.r. led drive tr.) ? adam41p2724 (excluding i.r. led drive tr .) ? adam41p2720 (excluding i.r. led drive tr.) september 26, 2012 ver 0.6 free datasheet http:///
page 1 of 54 instruction execution time 1us @ fosc =4mhz program memory (mtp) 48k bytes (24,576 x 16bit) [ multi - programmable by 1 6k - byte or 24k - byte ] data memory (ram) 256 nibble (256 x 4bit) 16 - bit table read instruction. 8 - level stack (including interrupts) timer timer / counter : 8bit * 2ch carrier generator : 6bit * 1ch watch dog timer : 19bit * 1ch oscillator type calibrated internal rcosc only : typ. 4mhz ( 2%) built in tr. for i.r. led drive in the adam41p2727/2723/2721 iol = 250ma at vdd=3v and vo=0.3v power on reset power saving operation modes stop 3 interrupt source operating voltage range 1.8v ~ 3.6v @4mhz low voltage detection circuit voltage detection indicator circuit : 2 - level [ 2.5v( 0.2v) / 2.1v( 0.2v) ] package 20sop/ 24sop / 28sop / 28tssop 1. overview the adam41p272x is the high speed and low voltage operating 4 - bit single chip microcomputer. this chip contains adam41 core, rom, ram, input/output ports , two timer/counters, etc. the adam41p272x is mtp version. 1.1. features table 1.1 adam41p272x series members series adam41p2727 adam41p2728 adam41p2723 adam41p2724 ADAM41P2721 adam41p2720 program memory 24,576 x 16 24,576 x 16 24,576 x 16 data memory 256 x 4 256 x 4 256 x 4 i/o ports 8 8 7 input ports 4 4 4 output ports 14 10 7 package 28sop/tssop 24sop 20sop adam41p272x 1. overview free datasheet http:///
page 2 of 54 1.2. pin assignments ( top view ) adam41p2727 adam41p2728 (28 sop) (28 tssop) 3 4 5 6 7 8 9 10 12 2 1 11 22 21 20 19 18 17 16 15 23 24 13 14 26 25 27 28 gnd [sck] pe2 pe3 pa0 pa1 pa2 pa3 pb0/int pb1 pb2/t0 pb3/t1 pc0 pd0 pd1 vdd rout r00 r01 r02 r03 [vpp] r10 r11 r12 [sda] r13 pc2 pc1 pd3 pd2 adam41p2723 adam41p2724 (24 sop) 3 4 5 6 7 8 9 10 12 2 1 11 18 17 16 15 14 13 19 20 22 21 23 24 gnd [sck] pe2 pe3 pa0 pa1 pa2 pa3 pb0/int pb1 pb2/t0 pb3/t1 pc0 vdd rout r00 r01 r02 r03 [vpp] r10 r11 r12 [sda] r13 pc2 pc1 1. overview adam41p272x gnd [sck] pe2 pa0 pa1 pa2 pa3 pb0/int pb1 pb2/t0 pc0 ADAM41P2721 adam41p2720 ( 20 sop) 3 4 5 6 7 8 9 10 2 1 14 13 12 11 15 16 18 17 19 20 vdd rout r00 r01 r02 r03 [vpp] r10 r11 r12 [sda] r13 free datasheet http:///
page 3 of 54 1.3. block diagram note1> pd0~pd3 ports are not available in adam41p2724 and adam41p2723 note2> pd0~pd3, pe3, pb3, pc1~pc2 ports are not available in adam41p2720 and ADAM41P2721 rout pb2 / t0 pb3 / t1 pb0 / int r00~r03 vdd gnd r00 ~ r03 adam41 core ram (256nibble) watch dog timer timer & carry generator interrupt request key scan & input clock gen. & system control r0 port rom r10~r13 r1 port pa port pb port pc port pd port r10 ~ r13 pa0 ~ pa3 pb0 ~ pb3 pc0 ~ pc2 pd0 ~ pd3 pb0~pb3 pe port pe2 ~ pe3 internal rc oscillator (4.0mhz 2%) adam41p272x 1. overview free datasheet http:///
page 4 of 54 1.4. package dimension 28 sop pin dimension (dimensions in inch) 15 11 12 19 18 17 0.713max 0.697min 0.020max 0.013min 1 2 3 4 5 6 7 8 9 10 28 27 26 25 24 23 22 21 20 0.013max 0.008min 0.042max 0.016min outline (unit : inch) 0.419max 0.398min 0.299max 0.291min 0.106max 0.093min 0.018max 0.004min 0 - 8? 13 14 16 0.050bsc 1. overview adam41p272x 28 tssop pin dimension (dimensions in millimeter) free datasheet http:///
page 5 of 54 adam41p272x 1. overview 20 sop pin dimension (dimensions in inch) 0.512max 0.4961min 0.020max 0.013min 0.050bsc 1 2 3 4 5 6 7 8 9 10 20 19 1 8 17 16 15 14 13 12 11 0.0125max 0.0091min 0.042max 0.016min outline (unit : inch) 0.419max 0.398min 0.299max 0.291min 0.104max 0.093min 0.018max 0.004min 0 - 8? 24 sop pin dimension (dimensions in inch) 11 12 15 14 13 0.614max 0.598min 0.019max 0.0138min 1 2 3 4 5 6 7 8 9 10 24 23 22 21 20 19 18 17 16 0.0125max 0.009min 0.042max 0.016min outline (unit : inch) 0.419max 0.398min 0.299max 0.292min 0.104max 0.093min 0.018max 0.004min 0 - 8? 0.050bsc free datasheet http:///
page 6 of 54 1.5. pin function 1. overview adam41p272x pin name input output function @reset @stop r00 r01 r02 r03 input input input input - 4 - bit input port. - cmos input with pull - up resistor. - can be selectable as stop release input pin individually by user program. (it is released by l input at stop mode) input (with pull - up) - r10 r11 r12 r13 i/o i/o i/o i/o - 4 - bit i/o port. - cmos input with pull - up resistor. - pull - ups can be disabled by user program. - can be selectable as stop release input pin individually by user program. (it is released by l input at stop mode) - n - ch open drain output. - can be programmable as push - pull output individually. - each pin can be set and reset by r1 data register value. input (with pull - up) state of before stop pa0 pa1 pa2 pa3 output output output output - n - ch open drain output. - each pin can be set and reset by pa data register value. hi - z l level output pb0/int pb1 pb2/t0 pb3/t1 i/o i/o i/o i/o - 4 - bit i/o port. - cmos input with pull - up resistor. - pull - ups can be disabled by user program. - can be selectable as stop release input pin individually by user program. (it is released by l input at stop mode) - n - ch open drain output. - can be programmable as push - pull output individually. - direct driving of led(n - tr). - each pin can be set and reset by pb data register value. input (with pull - up) state of before stop pc0 pc1 pc2 output output output - n - ch open drain output. - can be programmable as push - pull output individually. - direct driving of led(n - tr). - each pin can be set and reset by pc, pd and pe data register value. hi - z state of before stop pd0 pd1 pd2 pd3 output output output output pe2 pe3 output output rout output - high current output with built - in tr. ( for adam41p2727/2723/2721 ) hi - z hi - z - high current output ( for adam41p2728/2724/2720 ) l output l output vdd power - positive power supply. - - gnd power - ground - - free datasheet http:///
page 7 of 54 1.6. port structure 1.6.1. r0 ports 1. overview pin name circuit type @ reset high - input (with pull - up) pad vdd r00 r01 r02 r03 gnd pull up resistor stop release selection to r00~r03 stop release 1.6.2. r1 ports pin name circuit type @ reset hi - z pad gnd pa0~pa3 data register stop 1.6.3. pa ports pin name circuit type @ reset high - input (with pull - up) r10 r11 r12 r13 direction register data bus pad data register open drain selection mux vdd gnd vdd pull - up selection pull up resistor stop release selection to r10~r13 stop release adam41p272x free datasheet http:///
page 8 of 54 1. overview 1.6.4. pb ports adam41p272x pin name circuit type @ reset high - input (with pull - up) pb0 / int pb1 direction register data bus pad data register open drain selection mux vdd gnd function selection schmitt trigger to pb0int vdd pull - up selection pull up resistor stop release selection to pb0~pb1 stop release direction register data bus pad data register open drain selection mux vdd gnd function selection vdd pull - up selection pull up resistor pb2 / t0 pb3 / t1 mux from pb2t0 from pb3t1 high - input (with pull - up) stop release selection to pb2~pb3 stop release note > pb3 ports is not available in adam41p2720 and ADAM41P2721 free datasheet http:///
page 9 of 54 1.6.5. pc/ pd/ pe ports 1. overview pin name circuit type @ reset hi - z pc0 ~ pc2 pd0 ~ pd3 pe2 ~ pe3 pad data register open drain selection vdd gnd note > pd0~pd3 ports are not available in adam41p2724 and adam41p2723 note2 > pc1, pc2, pd0~pd3, pe3 ports are not available in adam41p2720 and ADAM41P2721 adam41p272x 1.6.6. rout port for adam41p2727, adam41p2723 and ADAM41P2721 pin name circuit type @ reset hi - z rout internal signal rout gnd 1.6.7. rout port for adam41p2728, adam41p2724 and adam41p2720 pin name circuit type @ reset low level rout internal signal rout vdd gnd free datasheet http:///
page 10 of 54 1. overview 1.7.1. absolute maximum ratings (ta = 25 ) 1.7.2. recommended operating ranges 1.7. electrical characteristics parameter symbol ratings unit supply voltage v dd - 0.3 ~ +6.0 v input voltage v i - 0.3 ~ v dd + 0.3 v output voltage v o - 0.3 ~ v dd + 0.3 v storage temperature t stg - 65 ~ 150 power dissipation p d 700 ? * thermal derating above 25 : 6mw per degree rise in temperature. parameter symbol condition min. typ. max. unit supply voltage v dd f osc = 4mhz (temp = 25 ) 1.8 3.6 v f osc = 4mhz (temp = - 20 ~ 70 ) 2.0 3.6 v oscillation frequency f osc internal rc oscillator (vdd = 1.8 ~ 3.6v) (temp = - 20 ~ 70 ) 3.92 4.0 4.08 mhz operating temperature t opr - 20 70 adam41p272x free datasheet http:///
page 11 of 54 1. overview 1.7.3. dc characteristics (vdd = 1.8v~3.6v , gnd = 0v, ta = 25 ) parameter symbol condition specification unit min. typ. max. high level input voltage vih1 int 0.8vdd vdd v vih2 r0, r1, pb 0.7vdd vdd v low level input voltage vil1 int 0 0.2vdd v vil2 r0, r1, pb 0 0.3vdd v high level input leakage current iih r0, r1, pb vih = vdd 1 ? low level input leakage current iil r0, r1, pb ( without pull - up ) vil = 0v - 1 ? high level output voltage voh1 r1, pb, pc, pd, pe ioh = - 1 ? vdd - 0.4 v low level output voltage vol1 r1, pa iol = 1 ? 0.8 v vol2 pb, pc, pd, pe iol = 5 ? 0.8 v high level output leakage current iohl r1, pa, pb, pc, pd, pe voh = vdd 1 ? low level output leakage current ioll r1, pa, pb, pc, pd, pe vol = 0v - 1 ? high level output current ioh rout ( for adam41p2728/24/20 ) vdd = 3v voh = 2v - 30 - 12 - 5 ? low level output current iol1 rout ( for adam41p2728/24/20 ) vdd = 3v vol = 1v 0.5 5 ? iol2 rout ( for adam41p2727/23/21 ) vdd = 3v vol = 0.3v 250 ? input pull - up current ip r0, r1, pb vdd =3v 10 30 60 ? power supply current idd operating current f osc = 4mhz vdd = 3.6v 0.8 2.4 ? vdd = 1.8v 0.5 1.5 ? istop stop mode current oscillator stop vdd = 3.6v 2.5 8 ? vdd = 1.8v 0.5 1.5 ? ram retention supply voltage vret 0.7 v adam41p272x free datasheet http:///
page 12 of 54 1.7.4. ac characteristics (vdd = 1.8v ~ 3.6v , gnd = 0v, ta = 25 ) fig. 1.1 timing chart int 0.8vdd 0.2vdd t ih t il no. parameter symbol pin specification unit min. typ. max. 1 internal rcosc clock cycle time t cp - - 250 - ? 2 system clock cycle time t sys - - 1000 - ? 3 interrupt pulse width high t ih int 2 t sys 4 interrupt pulse width low t il int 2 t sys 1. overview adam41p272x free datasheet http:///
page 13 of 54 internal rc oscillator characteristics graphs (for reference only) 1. overview adam41p272x operating temperature vs. frequency (vdd=3.0v) -1% 0% 1% 2% -2% 3.88 3.92 3.96 4.00 4.04 4.08 4.12 -20 0 25 50 70 o perating temperature : t ( ) frequency: fosc (mhz) operating voltage vs. frequency (temp=25) -2% -1% 0% 1% 2% 3.88 3.92 3.96 4.00 4.04 4.08 4.12 3.6 3.3 3.0 2.7 2.4 2.1 1.8 o perating voltage: vdd (v) frequency: fosc (mhz) free datasheet http:///
page 14 of 54 2. function description 2.1. program memory the adam41p272x can incorporate maximum 48k bytes (24k 16bits) for program memory. program counter pc (a0~a13) and page address register(a14) are used to address the whole area of program memory having an instruction (16bits) to be executed. the program memory consists of 16k words on 0 - page and 8k words on 1 - page. the program memory is composed as shown below. fig. 2.1 configuration of program memory 2. function description adam41p272x program counter (pc) page - 1 (8k words x 16bit) sfr (level1) (level2) (level3) interrupt stack register ( intsk ) (level1) (level2) (level3) (level4) (level5) stack register ( sr ) 14 4 page address register (pg) page - 0 (16k words x 16bit) 1 1 0 page buffer (pb) a14 a13 ~ a0 1 (level6) (level7) (level8) free datasheet http:///
page 15 of 54 2. function description 2.2. address register the following registers are used to address the rom. ? page address register (pg) : holds roms page number (0page, 1page) to be addressed. ? page buffer register (pb) : value of pb is loaded by an lpg command when newly addressing a page. then it is shifted into the pg when rightly executing a branch instruction (br) and a subroutine call (cal). ? program counter (pc) : available for addressing word on each page. ? stack register (sr) : stores returned - word address in the subroutine call mode. 2.2.1. page address register (pg) and page buffer register (pb) address one of 0 page to 1 page in the rom by the 1 - bit page address register. unlike the program counter, the page address register is usually unchanged so that the program will repeat on the same page unless a page changing command is issued. to change the page address, take two steps such as (1) writing in the page buffer what page to jump (execution of lpg) and (2) execution of br or cal, because instruction code is of eight bits so that page and word can not be specified at the same time. in case a return instruction (ret) is executed within the subroutine that has been called in the other page, the page address will be changed at the same time. 2.2.2. program counter (pc) this 14 - bit binary counter increments is for fetching a word to be addressed in the currently addressed page having an instruction to be next executed. for easier programming, at turning on the power, the program counter is reset to the zero location(0000h). the pg is also set to 0. then the program counter specifies the next address. when br, cal or ret instructions are decoded, the switches on each step are turned off not to update the address. then, for br or cal, address data are taken in from the instruction operands (a0 to a13), or for ret, and address including page address is fetched from stack register no. 1. adam41p272x free datasheet http:///
page 16 of 54 2.2.3. stack register (sr) the stack register provides two stages each for the program counter (14bits) and the page address register (1bit) so that subroutine nesting can be made on eight levels. the address stack register (ads) stores a return address when the subroutine call instruction is executed or interrupt is acknowledged. if subroutine or interrupts are nested to more than 8 levels, internal reset is occurred. the interrupt stack register(intsk) saves the contents of status flag register (sfr) when an interrupt is acknowledged. the saved contents are restored when an interrupt return(reti) instruction is executed. intsk saves data each time an interrupt is acknowledged. the programmer must keep in mind that the level of intsk is only 3. so, if more over 3 levels of interrupt occur, the first stored data is lost. there is different result between stack overflow and interrupt stack overflow. when clearing sp (stack pointer) with using spc instruction, interrupt processing must be inhibited before spc. 2. function description adam41p272x free datasheet http:///
page 17 of 54 2.3. data memory (ram) 256 nibbles (256 4bits) is incorporated for storing data. data address point (dp) fig. 2.2 data memory dp7~dp4 4 (256 x4bit) dp3~dp0 2.3.1. data memory (ram) addressing method 4 3 0 7 4 3 0 x x - register (ram index register) data address point (dp) 3 0 7 4 indexed data address point 3 0 y y - register (ram index register) the whole data memory area is directly addressed by 8 - bit ram data address point (dp). index data memory addressing is available using x - register and y - register. in this case, x - register is added upper 4bit of data point and y - register is added lower 4bit of data point. + + 2. function description 0 3 4 7 adam41p272x free datasheet http:///
page 18 of 54 below program example is guidance for understanding the flow of index data memory addressing. mem0 equ 033h ; defining ram address ldm mem0,#0ah ; [33h] = #0ah ldy #7 ; setting y register as #07h ldx #1 ; setting x register as #01h lda mem0 ; a = #0ah == [mem0] eix ; index enable ldm mem0,a ; [4ah] == [indexed addressed ram] = a dix ; index disable result after executing is mem0 = #0ah [mem0 + x + y] = = [4ah] = #0ah y + x + mem0 0ah 2.3.2. data memory(ram) data addressing example program fig. 2.3 data memory map 2. function description adam41p272x free datasheet http:///
page 19 of 54 2.4. general function registers 2.4.1. x - register (x) x - register consist of 4 bits. it can be used for a general - purpose register and also for data memory indexing register. 2.4.2. y - register (y) y - register consist of 4 bits. it can be used for a general - purpose register and also for data memory indexing register. 2.4.3. accumulator (acc) the 4 - bit register for holding data and calculation results. 2.4.4. peripheral address register (par) the 6 - bit address register for addressing peripheral registers including address buffer register (abr), data buffer register (dbr). 2.4.5. address buffer register (abr) the 15 - bit register for address buffer. it is composed of 3 registers(abr0, abr1, abr2) x 4bit and 1 register(abr3) x 3bit. 2. function description adam41p272x free datasheet http:///
page 20 of 54 data buffer register (dbr) 2.5. buffer registers (dbr,abr) buffer registers are two types of 16 bit registers composed of 4 nibble registers. one is data buffer register (dbr) and the other is address buffer register (abr). the address of data buffer register (dbr) is 3ch ~ 3fh and the address of address buffer register (abr) is 38h ~ 3bh on the peripheral register. these buffers are mainly used for data transferring between rom and buffer or peripheral registers and buffer. they are also used for general purpose register for data manipulation, data storage and intermediate buffer. 2.5.1. function of data buffer register(dbr) the most important function of dbr is intermediate (window) buffer for transferring data between peripheral registers and reading data from rom. when the data of rom is read by ldw @abr, one word of rom is fetched to dbr. the msb of rom data is written to dbr3 and lsb to dbr0. if the data of pointed rom is 1234h, each dbr has the data as dbr0 = 4h, dbr1 = 3h, dbr2 = 2h and dbr3 = 1h. dbr is also used for reading some peripheral register data by 8bit unit. the peripheral registers are t0cr and t1cr. 2.5.2. function of address buffer register (abr) the most important function of abr is rom address pointer. abr must be used for reading data from rom. the data pointed by abr is read to dbr. abr value is varied through peripheral control instruction and inc abr. internal bus program memory (rom) fig. 2.4 the internal data flow among dbr, abr , registers and rom peripheral address ; dbr0=3ch,dbr1=3dh dbr2=3eh,dbr3=3fh 8 bit timer (t0cr, t1cr) address buffer register (abr) peripheral address ; abr0=38h,abr1=39h abr2=3ah,abr3=3bh peripheral address ; t0crh=1fh, t0crl=20h t1crh=23h, t1crl=24h peripheral register. (the registers available r/w) accumulator (acc) 2. function description ldw @abr note > hex. file maps the data as big endian type. be careful to read the rom data. when the programmer assigns the data like below, the rom data is mapped as below db 12h,34h ? rom data = 1234h constant data adam41p272x free datasheet http:///
page 21 of 54 c arry flag in d ex flag i nterrupt enable flag s tatus flag 3 0 sfr status flag register s i d c 2.6.1. c arry flag ( c ) - carry flag bit is set when there is carry or borrow after executing addc / subc / arrc / arlc instructions. - set by setc and clear by clrc. 2.6.2. in d ex flag ( d ) - the control bit of ram data address point indexed or not. - x - register and y - register is used for index addressing. - set and cleared by eix, dix. 2.6.3. i nterrupt enable flag ( i ) - master enable flag of interrupt. - set and cleared by ei, di - this flag immediately becomes 0 when an interrupt is served. 2.6.4. s tatus flag ( s ) - according to the condition after executing an instruction , set or clear. - can not be set or clear by any instruction. - this flag decides whether operation of br and call would be done or not. 2.6. status flag register (sfr) status flag register (sfr) consists of 4 - bit register. each of the flags show the post state of operation and the flags determining the cpu operation, initialized as 0h in reset state. when an interrupt is occurred, the value of sfr keep the value of pre - interrupt except for i flag. so, be careful to initialize the sfr status for getting reliable result in interrupt sub - routine. 2. function description adam41p272x free datasheet http:///
page 22 of 54 2.7. peripheral registers note1> - is reserved bit , it must be read to 0. 2. function description adam41p272x peripheral address function registers read write symbol reset value 3 2 1 0 02 h port r1 pull up resistor selection reg. w r1pu 0 04 h port r1 data reg. r/w r1 f 01 h port r1 stop release selection reg. w r1st 0 05 h 08 h port pb open drain selection reg. w pbod 0 09 h port pb data reg. r/w pb f 07 h port pa data reg. r/w pa f 0a h port pb function selection reg. w pbfn 06 h port r1 direction reg. w r1dd 0 0 0 - 0 00 h port r0 stop release selection reg. w r0st 0 0b h port pc open drain selection reg. w pcod 0 0c h port pc data reg. r/w pc f 0d h port pd open drain selection reg. w pdod 0 0e h port pd data reg. r/w pd f 0f h 10 h 11 h reserved 12 h reserved 13 h port pe open drain selection reg. w peod 0 14 h port pe data reg. r/w pe f 15 h reserved 16 h reserved 03 h port r1 open drain selection reg. w r1od 0 rout control reg . r/w rcr 1c h 17 h 18 h int. enable reg. r/w ienr 19 h int. request flag reg. r/w irqr timer0 mode reg. r/w t0mr 1a h timer1 mode reg. r/w t1mr 1b h 0 0 0 0 0 0 0 0 0 0 0 timer 0 data0 high reg. w t0d0h 1f h carry mode reg. r/w cgmr 1e h 0 undefined 1d h voltage detection indicator register r vdir external int. edge selection reg. w ieds timer 0 count reg. high. r t0crh undefined port pb pull up resistor selection reg. w pbpu 0 port pb stop release selection reg. w pbst f port pb direction reg. w pbdd 0 - - 0 0 port r0 data reg. r r0 f - - 0 0 free datasheet http:///
page 23 of 54 2. function description adam41p272x note1> - is reserved bit , it must be read to 0. x is undefined bit. peripheral address function registers read write symbol 2a h 2b h 2c h reserved 2d h reserved 2e h reserved timer 1 high data reg. w t1hd 22 h timer 1 low data reg. w t1ld 23 h 24 h 25 h carry generator high - msb data reg. w cghmd 26 h carry generator high - lsb data reg. w cghld 27 h carry generator low - msb data reg. w cglmd 28 h carry generator low - lsb data reg. w cglld 29 h 2f h reserved reset value 3 2 1 0 undefined undefined undefined undefined undefined undefined 30 h 31 h 32 h 33 h 34 h 35 h reserved 36 h reserved 37 h reserved timer 0 data 1 high reg. w t0d1h timer 0 data 1 low reg. w t0d1l 21 h undefined undefined 38 h address buff register 0 r/w abr0 39 h address buff register 1 r/w abr1 undefined undefined 3a h address buff register 2 r/w abr2 3b h address buff register 3 r/w abr3 3c h data buff register 0 r/w dbr0 3d h data buff register 1 r/w dbr1 undefined undefined undefined undefined 3e h data buff register 2 r/w dbr2 3f h data buff register 3 r/w dbr3 undefined undefined 20 h reserved reserved reserved reserved reserved reserved reserved timer 0 data 0 low reg. w t0d0l undefined timer 0 count reg. low. r t0crl undefined timer 1 count reg. high. r t1crh undefined timer 1 count reg low. r t1crl undefined reserved x - x x free datasheet http:///
page 24 of 54 the adam41p272x has maximum 25 input or output ports which are r0 (4 input), r1 (4 i/o), pa (4 output), pb (4 i/o), pc (3 output), pd (4 output), pe(2 output). r0, r1 and pb input port have stop release selection register. pull - up resistors of r1 and pb port can be selectable by program. r1 and pb port contains data direction register which controls i/o and data register which stores port data. r1, pa, pb, pc, pd, pe ports have open drain output selection register. 3. i/o ports 3.1. port r0 r0 data register (r0) is 4 - bit register to store data of port r0. since r0 port is input only port, input state of pin is read. the initial value of r0 is fh in reset state. 3.1.1. r0 data register (r0) bit 3 2 1 r0 initial value r/w 0 00h r03 r02 r01 r00 1 r 1 r 1 r 1 r r0 stop release selection register (r0st) is 4 - bit register and can assign stop release pin or not. if r0st is selected as 0, stop release function is enabled and if selected as 1, it is disabled. r0st is write - only register and initialized as 0h in reset state. 3.1.1. r0 stop release selection register (r0st) bit 3 2 1 r0st initial value r/w 0 00h r0st3 r0st2 r0st1 r0st0 0 w 0 w 0 w 0 w 3. i/o ports 3.2. port r1 r1 stop release selection register (r1st) is 4 - bit register and can assign stop release pin or not. if r1st is selected as 0, stop release function is enabled and if selected as 1, it is disabled. r1st is write - only register and initialized as 0h in reset state. 3.2.1. r1 stop release selection register (r1st) bit 3 2 1 r1st initial value r/w 0 01h r1st3 r1st2 r1st1 r1st0 0 w 0 w 0 w 0 w r1 pull - up resistor control register (r1pc) is 4 - bit register and can control pull - up on or off each port, if corresponding port is selected as input. if r1pc is selected as 0, pull - up is enabled and if selected as 1, it is disabled. r1pc is write - only register and initialized as 0h in reset state. the pull - up is automatically disabled, if corresponding port is selected as output. 3.2.2. r1 pull - up resistor control register (r1pc) bit 3 2 1 r1pc initial value r/w 0 02h r1pc3 r1pc2 r1pc1 r1pc0 0 w 0 w 0 w 0 w adam41p272x free datasheet http:///
page 25 of 54 3. i/o ports r1 i/o data direction register (r1dd) is 4 - bit register, and can assign input state or output state to each bit. if r1dd is 0, port r1 is in the input state, and if 1, it is in the output state. r1dd is write - only register. since r1dd is initialized as 0h in reset state, the whole port r1 becomes input state. 3.2.5. r1 i/o data direction register (r1dd) bit 3 2 1 r1dd initial value r/w 0 05h r1dd3 r1dd2 r1dd1 r1dd0 0 w 0 w 0 w 0 w 3.2.3. r1 open drain assign register (r1od) bit 3 2 1 r1od initial value r/w 0 03h r1od3 r1od2 r1od1 r1od0 0 w 0 w 0 w 0 w r1 open drain assign register (r1od) is 4 - bit register, and can assign r1 port as open drain output port for each bit. if r1od is selected as 0, port r1 is open drain output, and if selected as 1, it is push - pull output. r1od is write - only register and initialized as 0h in reset state. 3.2.4. r1 data register (r1) r1 data register (r1) is 4 - bit register to store data of port r1. when set as the output state by r1dd, written data in r1 is outputted through r1 pin. when set as the input state, input state of pin is read to r1. the initial value of r1 is fh in reset state. bit 3 2 1 r1 initial value r/w 0 04h r13 r12 r11 r10 r/w 1 r/w 1 r/w 1 r/w 1 3.3. port pa 3.3.1. pa data register (pa) pa data register (pa) is 4 - bit register to store data of port pa. the initial value of pa is fh in reset state. bit 3 2 1 pa initial value r/w 0 07h pa3 pa2 pa1 pa0 r/w 1 r/w 1 r/w 1 r/w 1 adam41p272x free datasheet http:///
page 26 of 54 3.4. port pb pb pull - up resistor control register (pbpc) is 4 - bit register and can control pull - up on or off each bit, if corresponding port is selected as input. if pbpc is selected as 0, pull - up is enabled and if selected as 1, it is disabled. pbpc is write - only register and initialized as 0h in reset state. the pull - up is automatically disabled, if corresponding port is selected as output. 3.4.2. pb pull - up resistor control register (pbpc) bit 3 2 1 pbpc initial value r/w 0 09h pbpc3 pbpc2 pbpc1 pbpc0 0 w 0 w 0 w 0 w pb stop release selection register (pbst) is 4 - bit register, and can assign stop release pin or not. if pbst is selected as 0, stop release function is enabled and if selected as 1, it is disabled. pbst is write - only register and initialized as fh in reset state. 3.4.1. pb stop release selection register (pbst) bit 3 2 1 pbst initial value r/w 0 08h pbst3 pbst2 pbst1 pbst0 1 w 1 w 1 w 1 w 3.4.3. pb open drain assign register (pbod) bit 3 2 1 pbod initial value r/w 0 0ah pbod3 pbod2 pbod1 pbod0 0 w 0 w 0 w 0 w pb open drain assign register (pbod) is 4 - bit register, and can assign pb port as open drain output port for each bit. if pbod is selected as 0, port pb is open drain output, and if selected as 1, it is push - pull output. pbod is write - only register and initialized as 0h in reset state. pb data register (pb) is 4 - bit register to store data of port pb. the initial value of pb is fh in reset state. 3.4.4. pb data register (pb) bit 3 2 1 pb initial value r/w 0 0bh pb3 pb2 pb1 pb0 1 r/w 1 r/w 1 r/w 1 r/w pin name port selection function selection pb0 / int pb1 pb2 / t0 pb3 / t1 pb0 (i/o) pb1 (i/o) pb2 (i/o) pb3 (i/o) int input - timer 0 output timer 1 output 3. i/o ports adam41p272x free datasheet http:///
page 27 of 54 pb function selection register (pbfn) is 4 - bit register, and can assign the function mode for each bit. when set as 0, corresponding bit of pbfn acts as port pb selection mode, and when set as 1, it becomes function selection mode. selection mode of pbfn 3.4.5. pb function selection register (pbfn) bit 3 2 1 pbfn initial value r/w 0 0ch t1s t0s - ints 0 w 0 w pbfn is write - only register and initialized as 0h in reset state. therefore, becomes i/o port mode. pb i/o data direction register (pbdd) is 4 - bit register, and can assign input state or output state to each bit. if pbdd is 0, port pb is in the input state, and if 1, it is in the output state. pbdd is write - only register. since pbdd is initialized as 0h in reset state, the whole port pb becomes input state. 3.4.6. pb i/o data direction register (pbdd) bit 3 2 1 pbdd initial value r/w 0 0dh pbdd3 pbdd2 pbdd1 pbdd0 0 w 0 w 0 w 0 w 0 w 0 w bit name pmr1 selection mode remarks t1s 0 pb3 select (i/o) - 1 timer1 output select (output) the output status is toggled (l<>h) every t1 output (refer to fig. 4.5) t0s 0 pb2 select (i/o) - 1 timer0 output select (output) the output status is same as t0 output (refer to fig. 4.4) ints 0 pb0 select (i/o) - 1 external interrupt select (input) - - - - 3. i/o ports note> reserved bit must be 0. adam41p272x free datasheet http:///
page 28 of 54 pc data register (pc) is 3 - bit register to store data of port pc. the initial value of pc is fh in reset state. 3.5.2. pc data register (pc) bit 3 2 1 pc initial value r/w 0 0fh - pc2 pc1 pc0 1 - 1 r/w 1 r/w 1 r/w 3.5. port pc 3.5.1. pc open drain assign register (pcod) pc open drain assign register (pcod) is 3 - bit register, and can assign pc port as open drain output port for each bit. if pcod is selected as 0, port pc is open drain output, and if selected as 1, it is push - pull output. pcod is write - only register and initialized as 0h in reset state. bit 3 2 1 pcod initial value r/w 0 0eh - pcod2 pcod1 pcod0 - - 0 w 0 w 0 w 3.6.1. pd open drain assign register (pdod) bit 3 2 1 pdod initial value r/w 0 10h pdod3 pdod2 pdod1 pdod0 0 w 0 w 0 w 0 w pd open drain assign register (pdod) is 4 - bit register, and can assign pd port as open drain output port for each bit. if pdod is selected as 0, port pd is open drain output, and if selected as 1, it is push - pull output. pdod is write - only register and initialized as 0h in reset state. pd data register (pd) is 4 - bit register to store data of port pd. the initial value of pd is fh in reset state. 3.6.2. pd data register (pd) bit 3 2 1 pd initial value r/w 0 11h pd3 pd2 pd1 pd0 1 r/w 1 r/w 1 r/w 1 r/w 3.6. port pd 3. i/o ports adam41p272x free datasheet http:///
page 29 of 54 pe data register (pe) is 2 - bit register to store data of port pe. the initial value of pe is fh in reset state. 3.7.2. pe data register (pe) bit 3 2 1 pe initial value r/w 0 14h pe3 pe2 - - 1 r/w 1 r/w 1 - 1 - 3.7. port pe 3.7.1. pe open drain assign register (peod) pe open drain assign register (peod) is 2 - bit register, and can assign pe port as open drain output port for each bit. if peod is selected as 0, port pe is open drain output, and if selected as 1, it is push - pull output. peod is write - only register and initialized as 0h in reset state. bit 3 2 1 peod initial value r/w 0 13h peod3 peod2 - - 0 w 0 w - - - - 3. i/o ports adam41p272x free datasheet http:///
page 30 of 54 fig. 4.1 oscillator configurations 4. peripheral hardware 4.2. watch dog timer (wdt) fig. 4.2 block diagram of watch dog timer (wdt) watch dog timer (wdt) is organized binary of 19 steps. the signal of f osc /4 cycle comes in the first step of wdt after wdt reset. if the last step would be 1, reset signal automatically comes out and internal circuit is initialized. the overflow time is 2 18 4/f osc (262.144ms at f osc = 4.0mhz). normally, the binary counter must be reset before the overflow by using reset instruction (wdtc), power - on reset pulse or low vdd detection pulse. * it is constantly reset in stop mode. when stop is released, counting is restarted. adam41p272x internal rc oscillator circuit ring oscillator 4mhz clock from oscillation circuit makes cpu clock via clock pulse generator, and then provide peripheral hardware clock. binary counter(19 steps) reset by instruction (wdtc) f osc /4 power - on reset stop mode 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 cpu reset 1 reset (edge - trigger) 18 19 4. peripheral hardware 4.1. oscillation circuit there is only 1 type of oscillation circuit. it is internal rc oscillator circuit. the internal oscillator is calibrated in the otp writer. in stop mode, internal rc oscillator is stopped. free datasheet http:///
page 31 of 54 4.3. timer 4.3.1. timer operation mode timer is basically made of timer data register, timer mode register and control circuit. the types of timer are 8bit binary counter timer0 (t0), 8bit binary counter timer1 (t1), carrier generator (cg). timer0 data register consists of timer0 data 0 high register (t0d0h), timer0 data 0 low register (t0d0l), timer0 data 1 high register (t0d1h) and timer0 data 1 low register (t0d1l). timer1 data register consists of timer1 low data register (t1ld), timer1 high data register (t1hd). carrier generator consists of carrier generator high msb data register (cghmd), carrier generator high lsb data register (cghld), carrier generator low msb data register (cglmd) and carrier generator low lsb data register (cglld). fig. 4.3 timer / counter block diagram - 8 - bit interval timer - 8 - bit rectangular - wave output - 8 - bit interval timer - 8 - bit rectangular - wave output timer0 timer1 - 6 - bit up - counter - 6 - bit rectangular - wave output carrier generator 4. peripheral hardware adam41p272x rout t0 out / pb2 timer0 (8 bit) polarity selection t0hmd (4) t0hld (4) t0lmd (4) t0lld (4) tout logic (4) (4) (4) (4) (8) (8) carrier generator (6 bit) cghmd (2) cghld (4) cglmd (2) cglld (4) (2) (4) (2) (4) (6) (6) t1 out / pb3 timer1 (8 bit) t1hd (4) t1ld (4) (4) (4) (8) ** ** ** ** ** ** caution : the value of timer data register must be over 0 for correct timer operation tcarry carrier free datasheet http:///
page 32 of 54 4.3.2. function of timer & counter fig. 4.4 block diagram of timer0 (*) resolution & max. count of tcarry clock is decided by output of carrier generator 4. peripheral hardware t0mr [r/ w ] 1f h 0 1 t0if timer0 count reg high (t0crh) timer0 count reg low (t0crl) 20 h 1f h 20 h 21 h 22 h timer0 data 0 high reg timer0 data 0 low reg timer0 data 1 high reg timer0 data 1 low reg 3 2 1 0 1a h ck mux int. gen. data bus (8) (8) (8) (8) tck1 tck2 mux tck3 tcarry timer0 data 0 high buffer timer0 data 0 low buffer timer0 data 1 high buffer timer0 data 1 low buffer t0ck ** every 2nd counter overflow t0cs t0ck output gen. t0 counter (8 bit) t0 output (8 2 ) note> the status of t0 output is 0 for counting t0d0 data reg and 1 for counting t0d1 data reg. f osc = 4mhz 8bit timer (timer0) 8bit timer (timer1) carrier generator (cg) resolution (ck) max. count resolution (ck) max. count resolution (ck) max. count tck1 tck2 : 0. 5 us : 1 us 128 us 256 us tck3 : 2 us 512 us tck1 tck2 : 1 us 256 us tck3 : 2 us 512 us tck1 tck2 : 0. 5 us : 1 us 32 us 64 us tck3 tck4 : 2 us : 4 us 128 us 256 us tcarry(*) tcarry(*) : 0.5 us 128 us adam41p272x free datasheet http:///
page 33 of 54 fig. 4.6 block diagram of carrier generator fig. 4.5 block diagram of timer1 4. peripheral hardware carrier output (tcarry) 25 h 26 h 27 h 28 h carry hm data reg carry hl data reg carry lm data reg carry ll data reg 1e h mux data bus (6) (6) tck1 tck2 cgmr [ r/w ] 3 2 1 0 mux ck tck3 tck4 carrier counter (6 bit) 1 0 output gen. t1mr [r/w ] 23 h t1if timer1 count reg high (t1crh) 23 h 24 h timer1 high data reg timer1 l0w data reg 3 2 1 0 1c h t1 counter (8 bit) ck int. gen. t1 output data bus (8) 24 h timer1 count reg low (t1crl) tck1 tck2 mux tck3 tcarry ** every counter overflow output gen. (toggled) (8) note> the status of t1 output is toggled 0 to 1 or 1 to 0 at every output gen. adam41p272x free datasheet http:///
page 34 of 54 bit 3 2 1 t0mr [r/w ] 0 1ah t0cs t0cn t0ck1 t0ck0 4.3.2.1. timer0 mode register initial value r/w 0 r/w 0 r/w 0 r/w 0 r/w 4. peripheral hardware * timer 0 counts with t0d0h+t0d0l first , after overflowed counts with t0d1h+t0d1l t0cn 0 1 timer0 pause / continue control timer0 pause timer0 continue t0cs 0 1 timer0 clear / start control timer0 stop timer0 clear and start t0ck1 & t0ck0 00 01 10 11 input clock selection tck1 (500ns) tck3 (2us) tck2 (1us) tcarry (output of carrier generator) bit 3 2 1 t1mr [r/w ] 0 1ch t1cs t1cn t1ck1 t1ck0 t1ck1 & t1ck0 input clock selection 00 01 10 11 tck2 (1us) tck1 (500ns) tck3 (2us) tcarry (output of carrier generator) t1cn 0 1 timer1 pause / continue control timer1 pause timer1 continue t1cs 0 1 timer1 clear / start control timer1 stop timer1 clear and start 4.3.2.2. timer1 mode register initial value r/w 0 r/w 0 r/w 0 r/w 0 r/w adam41p272x 4.3.2.3. carrier generator mode register cgck1 & cgck0 00 01 10 11 input clock selection tck1 (500ns) tck3 (2us) tck2 (1us) tck4 (4us) cgon 0 1 carrier generator output control output of rout without carrier pulse output of rout with carrier pulse cgcs 0 1 carrier generator clear / start control carrier generator stop carrier generator clear and start cgmr [r/w ] 1eh cgcs cgon cgck1 cgck0 initial value r/w 0 r/w 0 r/w 0 r/w 0 r/w free datasheet http:///
page 35 of 54 4. peripheral hardware * rout pin is controlled by rem when pron bit =0 * rout pin is controlled by pr0, pr1 when pron bit =1 because timer0 counts with data0 (t0d0h+t0d0l) first , rout pin is controlled by pr0 initially. adam41p272x rem output of rout bit control (when pron=0) 0 rout output hi - z [ rout output low ] 1 rout output low [ rout output high ] pron pr0 / pr1 function control 0 pr0 / pr1 function disable (rem bit active) 1 pr0 / pr1 function enable (rem bit inactive) pr0 preset of rout bit control (when pron=1) 0 rout h on counting timer0 data0 (t0d0h + t0d0l) [ rout l on counting timer0 data0 (t0d0h + t0d0l) ] 1 rout l on counting timer0 data0 (t0d0h + t0d0l) [ rout h on counting timer0 data0 (t0d0h + t0d0l) ] pr1 preset of rout bit control (when pron=1) 0 rout h on counting timer0 data1 (t0d1h + t0d1l) [ rout l on counting timer0 data1 (t0d1h + t0d1l) ] 1 rout l on counting timer0 data1 (t0d1h + t0d1l) [ rout h on counting timer0 data1 (t0d1h + t0d1l) ] bit 3 2 1 rcr [r/w ] 0 1dh pr1 pr0 pron rem 4.3.2.4. rout control register initial value r/w 0 r/w 0 r/w 0 r/w 0 r/w fig. 4.7 flow of controlling rout pr1 pr0 pron rem rcr [r/w] 1dh buffer ck t0ck 1 0 0 1 t0 output rout gen. carrier cgon rout * [ ] for adam41p2728/24/20 free datasheet http:///
page 36 of 54 4.3.2.5. control of rout with using timer0 ( for the case of adam41p2728/24/20 ) 4. peripheral hardware adam41p272x cgh = #9 cgl = #17 t0mr = #0 t0d0 = #100 t0d1 = #100 rcr = #0110b cgmr = #1101b t0mr = #1101b ; 9u carrier high ; 17u carrier low -- > 38khz ; stop timer0 ; presetting a status of rout ; presetting the length of the pulse ; presetting rout status(high on t0d0, low on t0d1) ; carrier clear and start /rout with carrier/1usec resolution ; start timer0 for making 100usec high and low t0d1 = #100 t0d0 = #50 rcr = #0110b t0if = 1 1 ; presetting b status of rout ; presetting the next length of the pulse ; presetting the next rout status (high on t0d0, low on t0d1) t0d1 = #100 t0d0 = #50 rcr = #0110b t0if = 1 2 2 ; presetting c status of rout ; presetting the next length of the pulse ; presetting the next rout status (high on t0d0, low on t0d1) t0d1 = #200 t0d0 = #100 rcr = #0010b t0if = 1 3 3 ; presetting delay of c status of rout because low is longer than 255 ; presetting the next length of the pulse ; presetting the next rout status (low on t0d0, low on t0d1) a b c t0d1 = #100 t0d0 = #50 rcr = #0110b t0if = 1 4 4 n n n n y y y y y the status of rout 1 ; presetting d status of rout ; presetting the next length of the pulse ; presetting the next rout status (high on t0d0, low on t0d1) 100us 100us 50us 100us 50us 50us 50us 400us a b c 100us d note> waveform is modulated with 38khz carrier. rout free datasheet http:///
page 37 of 54 4.3.3. timer0 fig. 4.8 operation of timer0 clear t0 data registers value interval period t0 value 0 clear clear interrupt interrupt t0if (t0d0h+t0d0l) (t0d1h+t0d1l) (t0d1h+t0d1l) 4. peripheral hardware fig. 4.9 start / stop operation of timer0 t0if t0cs t0cn 0 1 clear & start stop clear & count count continue clear & start concurrence clear t0 data registers value concurrence t0 value 0 clear interrupt 0 1 counter count stop timer0 operates as a up - counter with two - 8bit data register (t0d0h+t0d0l, t0d1h+t0d1l). when the value of the up - counter reaches the content of timer data register, the up - counter is cleared to ``00 h``, and interrupt (t0if ) is occurred at the next clock. internal clock (tck) and the output of carrier generator (tcarry) is used as counter clock. the counter execution is controlled by t0cs, t0cn, of t0mr. t0cn is used to stop and start timer0 without clearing the counter and t0cs does to clear and start the counter. during counting - up, value of counter can be read. timer execution is stopped by the reset signal. adam41p272x free datasheet http:///
page 38 of 54 fig. 4.11 start / stop operation of timer1 4. peripheral hardware t1if t1cs t1cn 0 1 stop clear & count count continue clear & start concurrence clear t1 data registers value concurrence t1 value 0 clear interrupt interrupt 0 1 counter count stop clear & start timer1 operates as a up - counter. timer1 has 8bit data register (t1hd+t1ld). when the value of the up - counter reaches the content of timer data register, the up - counter is cleared to 00h, and interrupt (t1if ) is occurred at the next clock. internal clock (tck) and the output of carrier generator (tcarry) is used as counter clock. the counter execution is controlled by t1cs, t1cn, of t1mr. t1cn is used to stop and start timer1 without clearing the counter and t1cs does to clear and start the counter. during counting - up, value of counter can be read. timer execution is stopped by the reset signal. 4.3.4. timer1 fig. 4.10 operation of timer1 clear t1 data registers value interval period t1 value 0 clear clear interrupt interrupt t1if (t1hd+t1ld) interrupt (t1hd+t1ld) (t1hd+t1ld) adam41p272x free datasheet http:///
page 39 of 54 carrier generator operates as a up - counter. carrier generator has two 6bit - data register(cghmd+cghld, cglmd+cglld). the execution of carrier generator is controlled by cgf0,cgf1,cgon,cgcs of carrier generator mode register (cgmr). when cgcs is set to ``1``, count value of carrier generator is cleared and starts counting - up. carrier generator first counts cglmd+cglld and next cghmd+cghld. cglmd+cglld are for the pulse of the carrier (burst) and cglmd+cglld are for the low of the carrier (pause). fig. 4.13 start/stop of carrier generator 4.3.5. carrier generator fig. 4.12 operation of carrier generator 4. peripheral hardware cgcs 0 stop clear & start concurrence clear carrier generator data registers value concurrence carrier generator value 0 clear counter count clear & start 1 clear & start cghmd+cghld clear carrier generator data registers value cglmd+cglld cghmd+cghld carrier generator value 0 clear clear carrier generator output (carrier/ tcarry) pause burst adam41p272x free datasheet http:///
page 40 of 54 5. interrupt the adam41p272x contains 3 interrupt sources; 1 externals and 2 internals. nested interrupt services with priority control is also possible. ? 3 interrupt source (1ext, 2timer ) ? 3 interrupt vector ? 3 level nested interrupt control is possible. ? read of interrupt request flag are possible. ? in interrupt accept, request flag is automatically cleared. interrupt enable register (ienr), interrupt request register (irqr) and priority circuit. interrupt function block diagram is shown in fig. 5.1. fig. 5.1 interrupt source 5. interrupt irqr[r/w] inte t0e t1e standby mode release - 0 3 ienr [r/w] priority control int. vector addr. data bus intif 5.1. interrupt source each interrupt vector is independent and has its own priority. table 5.1 interrupt source mask priority interrupt source int vector addr. hardware interrupt maskable 2 3 t0e (timer0) t1e (timer1) 0006h 0008h non - maskable - reset 0000h 1 inte (external interrupt) 0002h adam41p272x - t0if t1if free datasheet http:///
page 41 of 54 i flag of sfr is a interrupt mask enable flag. when i flag = 0, all interrupts become disable. when i flag = 1, interrupts can be selectively enabled and disabled by contents of corresponding interrupt enable register(ienr). when interrupt is occurred, interrupt request flag is set,and interrupt request is detected at the edge of interrupt signal. the accepted interrupt request flag is automatically cleared during interrupt cycle process. the interrupt request flag maintains 1 until the interrupt is accepted or is cleared in program. in reset state, interrupt request flag register (irqr) is cleared to 0. it is possible to read the state of interrupt register and to manipulate the contents of register. 5.2. interrupt control register 5. interrupt external interrupt edge selection register bit 3 2 1 ieds [ w ] 0 17h - - ied1h ied1l initial value r/w 0 w 0 w 0 w 0 w note> reserved bit must be 0. iedh & iedl 00 - 01 falling edge selection 10 rising edge selection 11 both edge selection 5.2.1. interrupt timing interrupt request sampling time - maximum 2 machine cycles (when execute ldw @abr instruction) - minimum 0 machine cycle interrupt preprocess step is 1 machine cycle. i flag is valid just after executing of ei/di on the contrary. 5.2.2. the valid timing after executing interrupt control instructions t1e timer1 interrupt enable bit t0e timer0 interrupt enable bit - - inte ext. interrupt enable bit interrupt enable register 18h ienr - t1e t0e inte [ r/w ] bit 3 2 1 0 initial value r/w 0 r/w 0 r/w 0 r/w 0 r/w note> reserved bit must be 0. interrupt request flag register 19h irqr - t1f t0if intif [ r/w ] bit 3 2 1 0 initial value r/w 0 r/w 0 r/w 0 r/w 0 r/w note> reserved bit must be 0. t1if timer1 interrupt request flag bit t0if timer0 interrupt request flag bit - - intif ext. interrupt request flag bit adam41p272x free datasheet http:///
page 42 of 54 5. interrupt when an interrupt is accepted, the on - going process is stopped and the interrupt service routine is executed. after the interrupt service routine is completed it is necessary to restore everything to the state before the interrupt occurred. as soon as an interrupt is accepted, the content of the program counter is saved in the stack register and the contents of status flag register (sfr ) is saved into the interrupt stack register (intsk) which is 3 level stack area. at the same time, the content of the vector address corresponding to the accepted interrupt, which is in the interrupt vector table, enters into the program counter and interrupt service is executed. in order to execute the interrupt service routine, it is necessary to write the jump addresses in the vector table (0002 h ~ 0008 h) corresponding to each interrupt. 5.3. interrupt processing sequence interrupt processing step fig. 5. 2 interrupt processing step timing 5.4. multiple interrupt if there is an interrupt, interrupt mask enable flag is automatically cleared before entering the interrupt service routine. after then, no interrupt is accepted. if ei instruction is executed, interrupt mask enable bit becomes ``1``, and each enable bit can accept interrupt request. when two or more interrupts are generated simultaneously, the highest priority interrupt is accepted. system ck1 pc - 1 interrupt pc interrup t accept system ck2 system ck3 pc new pc interrupt vector addr interrup t control sp - 1 stack pointer sp adam41p272x 1) store program counter to stack, sp sp - 1 2) store the contents of status flag register (sfr) to intsk, spsfr spsfr - 1 3) after resetting of i - flag, clear accepted interrupt request flag. 4) call interrupt service routine free datasheet http:///
page 43 of 54 6. stop function 6. stop function stop mode can be entered by stop instruction during program. in stop mode, oscillator is stopped to make all clocks stop, which leads to less power consumption. all registers and ram data are preserved. nop instruction should be follows stop instruction for pre - charge time of data bus line. ex) stop : stop instruction execution nop : nop instruction 6.2. stop mode release release of stop mode is executed by power on reset , inputting low to key input port (one of r0, r1, pb) which is selected by r0st, r1st and pbst register for stop release, external interrupt and low voltage detection (lvd) mode release . when there is a release signal of stop mode, the instruction execution starts after oscillation stabilization time( 2 14 4/f osc = 16.384ms at f osc = 4.0mhz) table 6.2 stop mode release table 6.1 operation state in stop mode 6.1. stop mode release factor release method by power on reset, stop mode is release and system is initialized power on reset stop mode is released by low input of pin selected by r0st, r1st, pbst register r0, r1, pb port (key input) stop mode is released by external interrupt input external interrupt stop mode is released by lvd detection. release from lvd detection adam41p272x internal circuit stop mode oscillator stop internal cpu clock stop register retained ram retained ports r1,pb,pc,pd,pe ports retained pa port low rout port hi - z (for adam41p2727/23/21) low (for adam41p2728/24/20) timer stop voltage detection indicator stop watch dog timer reset and restart at stop release address bus, data bus retained free datasheet http:///
page 44 of 54 7. reset function power on reset circuit automatically detects the rise of power voltage (the rising time should be within 50ms). until the power voltage reaches a certain voltage level, internal reset signal is maintained at l level until internal oscillator is stable. after power applies and starting of oscillation, this reset state is maintained for about oscillation stabilization time of 2 16 x 4/fosc (about 65.536ms : at 4mhz). 7. reset function 7.1. power on reset fig. 7.1 block diagram of power on reset circuit power on detection circuit internal reset vdd internal ic adam41p272x free datasheet http:///
page 45 of 54 8. lvd mode 8. lvd (low voltage detection) mode 8.1. low voltage detection condition an on - board voltage comparator checks that v dd is at the required level to ensure correct operation of the device. if v dd is below a certain level, low voltage detector forces the device into low voltage detection mode. 8.2. low voltage detection mode there is no power consumption except stop current, stop mode release function is disabled. i/o port is configured as input mode(with pull - up resistor) and data memory is retained until voltage through external capacitor is worn out. in this mode, output ports( pa, pc, pd, pe) are configured open drain h output (pc, pd ports have push - pull h output by option) and i/o ports( r1 , pb) are fixed input with pull - up enabled (pull - up disable is option in lvd mode). 8.3. release of low voltage detection mode reset signal result from new battery (normally 3v) wakes the low voltage detection mode and come into normal reset state. it depends on user whether to execute ram clear routine or not. adam41p272x 8.4. voltage detection indicator register voltage indication can be checked by reading of the voltage detection indicator data register (vdir). it is useful to display the consumption of batteries. if vdd power level is low and higher than low voltage detection (lvd) level (refer to fig 9.1), the bit of vdir register could be set according to the vdd level sequentially. the vdd detection levels for indication are two, that is, vdir0, vdir1 of vdir register. the detection voltage level are vdir1 (typ. 2.5v) and vdir0(typ. 2.1v ). voltage detection indicator is always operating but it is stopped in the stop mode. in the in - circuit emulator, voltage detection indicator function is not implemented and user can not experiment with it. therefore after final development of user program, this function may be experimented or evaluated. bit 3 2 1 vdir [r/w ] 0 1bh - - vdir1 vdir0 8.4.1. voltage detection indicator data register (vdir) initial value r/w - - - - 0 r 0 r voltage detection indicator data register (vdir) is 2 - bit register to store data of low voltage level. vdir is read only register and initialized as 0h in reset state. free datasheet http:///
page 46 of 54 9. sram data back - up fig. 9.1 low voltage detection and protection fig. 9.2 s/w flow chart example for sram back - up 3.0v 1.7v(typ) ( 25 ) user removes batteries user replace batteries ? interrupt : disable ? stop release : disable ? all i/o port : input mode(with pull - up ) ? rout port : hi - z (for adam41p2727/23/21) : low (for adam41p2728/24/20) ? oscillator : stop ? output port : open drain output level h ? sram data : retention * the operation after low voltage detection mcu opr. voltage about hours depend on vdd - gnd capacitor * sram data backup power on reset ( sram retention) power on reset ( sram unstable ) low voltage detection point 0.7v (vret) 0.0v 9.2. s/w flow chart example after reset using sram data back - up n y reset stack pointer initialize check the sram value (ram pattern, checksum..) sram data is valid? use saved sram value clear all ram area 9.1. sram data back - up after low voltage detection 9. sram data back - up adam41p272x free datasheet http:///
page 47 of 54 10. mtp programming 10. mtp programming adam41p272x 10.1. pin assignment eprom mode ? user mode user mode ? eprom mode gnd sck - - - - - - - - - - - - vdd - - - - vpp - - sda - - - - - adam41p2727 adam41p2728 (28 sop) (28 tssop) 3 4 5 6 7 8 9 10 12 2 1 11 22 21 20 19 18 17 16 15 23 24 13 14 26 25 27 28 gnd pe2 pe3 pa0 pa1 pa2 pa3 pb0/int pb1 pb2/t0 pb3/t1 pc0 pd0 pd1 vdd rout r00 r01 r02 r03 r10 r11 r12 r13 pc2 pc1 pd3 pd2 eprom mode ? user mode user mode ? eprom mode gnd sck - - - - - - - - - - vdd - - - - vpp - - sda - - - adam41p2723 adam41p2724 (24 sop) 3 4 5 6 7 8 9 10 12 2 1 11 18 17 16 15 14 13 19 20 22 21 23 24 gnd pe2 pe3 pa0 pa1 pa2 pa3 pb0/int pb1 pb2/t0 pb3/t1 pc0 vdd rout r00 r01 r02 r03 r10 r11 r12 r13 pc2 pc1 free datasheet http:///
page 48 of 54 10. mtp programming adam41p272x 10. 2. pin function eprom mode ? user mode user mode ? eprom mode gnd sck - - - - - - - - vdd - - - - vpp - - sda - - - ADAM41P2721 adam41p2720 ( 20 sop) 3 4 5 6 7 8 9 10 2 1 14 13 12 11 15 16 18 17 19 20 gnd pe2 pa0 pa1 pa2 pa3 pb0/int pb1 pb2/t0 pc0 vdd rout r00 r01 r02 r03 r10 r11 r12 r13 symbol user mode eprom mode vdd power vdd power (typ. 5v) gnd ground gr ound (0v) vpp r03 program/verify power (t yp. 11.5v) sck osc1 serial clock input sda r12 serial data input / output (open - drain output) free datasheet http:///
page 49 of 54 10. mtp programming adam41p272x ? 15 bit for option bit are available. ? r1, pb ports have pull - up resistor or not at lvd mode ? pc, pd ports are push - pull high output or high - z(high - impedance output) at lvd mode. ? configuration option bit mapping list [address : 8400h] 10.3.1 . port status option at lvd mode bit initial value 15 - 1 8400h 14 pd2l 1 13 pd1l 1 12 pd0l 1 11 pc2l 1 10 1 9 pc1l 1 8 pc0l 1 7 pb3l 1 6 pb2l 1 5 pb1l 1 4 pb0l 1 3 r13l 1 2 r12l 1 1 r11l 1 0 r10l 1 pd3l bit name code write value option result initial value option description 1 (no writing =default) pd2l 0 1 pd2 port is push - pull high at lvd mode pd2 port is high - z at lvd mode pd2 is push - pull high or high - z at lvd mode 1 (no writing =default) pd1l 0 1 pd1 port is push - pull high at lvd mode pd1 port is high - z at lvd mode pd1 is push - pull high or high - z at lvd mode 1 (no writing =default) pd0l 0 1 pd0 port is push - pull high at lvd mode pd0 port is high - z at lvd mode pd0 is push - pull high or high - z at lvd mode 1 (no writing =default) pc2l 0 1 pc2 port is push - pull high at lvd mode pc2 port is high - z at lvd mode pc2 is push - pull high or high - z at lvd mode 1 (no writing =default) pc1l 0 1 pc1 port is push - pull high at lvd mode pc1 port is high - z at lvd mode pc1 is push - pull high or high - z at lvd mode 1 (no writing =default) pc0l 0 1 pc0 port is push - pull high at lvd mode pc0 port is high - z at lvd mode pc0 is push - pull high or high - z at lvd mode 1 (no writing =default) pb3l 0 1 pb3 has no pull - up resistor at lvd mode pb3 has pull - up resistor at lvd mode pb3 has pull - up resistor or not at lvd mode 1 (no writing =default) pb2l 0 1 pb2 has no pull - up resistor at lvd mode pb2 has pull - up resistor at lvd mode pb2 has pull - up resistor or not at lvd mode 1 (no writing =default) pb1l 0 1 pb1 has no pull - up resistor at lvd mode pb1 has pull - up resistor at lvd mode pb1 has pull - up resistor or not at lvd mode 1 (no writing =default) pb0l 0 1 pb0 has no pull - up resistor at lvd mode pb0 has pull - up resistor at lvd mode pb0 has pull - up resistor or not at lvd mode 1 (no writing =default) r13l 0 1 r13 has no pull - up resistor at lvd mode r13 has pull - up resistor at lvd mode r13 has pull - up resistor or not at lvd mode 1 (no writing =default) r12l 0 1 r12 has no pull - up resistor at lvd mode r12 has pull - up resistor at lvd mode r12 has pull - up resistor or not at lvd mode 1 (no writing =default) r11l 0 1 r11 has no pull - up resistor at lvd mode r11 has pull - up resistor at lvd mode r11 has pull - up resistor or not at lvd mode 1 (no writing =default) r10l 0 1 r10 has no pull - up resistor at lvd mode r10 has pull - up resistor at lvd mode r10 has pull - up resistor or not at lvd mode 1 (no writing =default) - - - - - - 1 (no writing =default) pd3l 0 1 pd3 port is push - pull high at lvd mode pd3 port is high - z at lvd mode pd3 is push - pull high or high - z at lvd mode 10.3. configuration option description free datasheet http:///
page 50 of 54 11.1. legend 11. instruction set a : accumulator(4bit) r : peripheral address register(6bit) [r] : data addressed by peripheral address register (4bit) y : y register(4bit) x : x register(4bit) abr : address buffer register(15bit) abrn : address buffer register #0~2(4bit), #3(3bit) [@abr] : data addressed by abr(16bit) dbr : data buffer register(16bit) dbrn : data buffer register #0~3(4bit) t0cr : timer 0 count register(8bit) t1cr : timer 1 count register(8bit) #n4 : 0~fh #n2 : 0~3 #n1 : 0~1 dp : data address point(8bit) dp+x+y : data address point indexed by x - register and y - register (8bit) m(dp) : data addressed by dp m(dp+x+y) : data addressed by dp+x+y pg : page address(1bit) ads : address stack register !abs : address 11. instruction set adam41p272x free datasheet http:///
page 51 of 54 11.2. instruction set table instruction group mnemonic usage opeation s cy 1 arithmatic addc addc m(dp),#n4 a = m(dp) + #n4 + cy a = m(dp+x+y) + #n4 + cy at d flag of sfr is set. s set if overflow c o 2 addc a,#n4 a = a + #n4 + cy, s set if overflow c o 3 addc m(dp),a a = m(dp) + a + cy a = m(dp+x+y) + a + cy at d flag of sfr is set. s set if overflow c o 4 addc abrn,#n4 abrn = abrn + #n4 + cy, s set if overflow c o 5 addc abrn,a abrn = abrn + a + cy, s set if overflow c o 6 addc abrn,y abrn = abrn + y + cy, s set if overflow c o 7 addc dbrn,#n4 dbrn = dbrn + #n4 + cy, s set if overflow c o 8 addc dbrn,a dbrn = dbrn + a + cy, s set if overflow c o 9 addc dbrn,y dbrn = dbrn + y + cy, s set if overflow c o 10 addc y,#n4 y = y + #n4 + cy, s set if overflow c o 11 addc x,#n4 x = x + #n4 + cy, s set if overflow c o 12 subc subc m(dp),#n4 a = m(dp) - #n4 - cy a = m(dp+x+y) - #n4 - cy at d flag of sfr is set. s clear if underflow b w 13 subc a,#n4 a = a - #n4 - cy, s clear if underflow b w 14 subc m(dp),a a = m(dp) - a - cy a = m(dp+x+y) - a - cy at d flag of sfr is set. s clear if underflow b w 15 subc abrn,#n4 abrn = abrn - #n4 - cy, s clear if underflow b w 16 subc abrn,a abrn = abrn - a - cy, s clear if underflow b w 17 subc abrn,y abrn = abrn - y - cy, s clear if underflow b w 18 subc dbrn,#n4 dbrn = dbrn - #n4 - cy, s clear if underflow b w 19 subc dbrn,a dbrn = dbrn - a - cy, s clear if underflow b w 20 subc dbrn,y dbrn = dbrn - y - cy, s clear if underflow b w 21 subc y,#n4 y = y - #n4 - cy, s clear if underflow b w 22 subc x,#n4 x = x - #n4 - cy, s clear if underflow b w 23 arrc arrc a = a rotate right with cy t r 24 arlc arlc a = a rotate left with cy t r 25 compare cale cale #n4 s set if a #n4 e 26 cale m(dp) s set if a m(dp) s set if a m(dp+x+y) at d flag of sfr is set. e 27 cane cane #n4 s set if a != #n4 n 28 cane m(dp) s set if a != m(dp) s set if a != m(dp+x+y) at d flag of sfr is set. n 11. instruction set adam41p272x free datasheet http:///
page 52 of 54 instruction group mnemonic usage opeation s cy 29 compare cmle cmle m(dp),#n4 s set if m(dp) #n4 s set if m(dp+x+y) #n4 at d flag of sfr is set. e 30 cmne cmne m(dp),#n4 s set if m(dp) != #n4 s set if m(dp+x+y) != #n4 at d flag of sfr is set. n 31 cyne cyne #n4 s set if y != #n4 n 32 cyne a s set if y != a n 33 cxne cxne #n4 s set if x != #n4 n 34 bit manipulation set1 set1 m(dp),#n2 set bit m(dp).#n2 set bit m(dp+x+y).#n2 at d flag of sfr is set. s 35 clr1 clr1 m(dp),#n2 clear bit m(dp).#n2 clear bit m(dp+x+y).#n2 at d flag of sfr is set. s 36 tm tm m(dp),#n2 s set if m(dp).#n2 = 1 s set if m(dp+x+y).#n2 = 1 at d flag of sfr is set. e 37 setr1 setr1 r,#n2 set bit [r].#n2 s 38 clrr1 clrr1 r,#n2 set bit [r].#n2 s 39 tstr tstr r,#n2 s set if [r].#n2 bit = 1 e 40 carry manipulation clrc clrc carry bit of sfr is clear s 41 setc setc carry bit of sfr is set s 42 tstc tstc s set if carry test = 1 e 43 data transfer ldm ldm m(dp),#n4 m(dp) = #n4 m(dp+x+y) = #n4 at d flag of sfr is set. s 44 ldm m(dp),a m(dp) a m(dp+x+y) a at d flag of sfr is set. s 45 lda lda #n4 a = #n4 s 46 lda m(dp) a m(dp) a m(dp+x+y) at d flag of sfr is set. s 47 lda x a x s 48 lda y a y s 49 ldy ldy #n4 y = #n4 s 50 ldy a y a s 51 ldx ldx #n4 x = #n4 s 52 ldx a x a s 53 xma xma m(dp) a ? m(dp) a ? m(dp+x+y) at d flag of sfr is set. s 54 ldw ldw @abr dbr [@abr] **[note] s 55 ldw dbr,abr dbr abr s 56 ldw abr,dbr abr dbr s 57 ldw dbr,t0cr dbr0,drb1 t0cr s 58 ldw dbr,t1cr dbr0,dbr1 t1cr s 11. instruction set adam41p272x free datasheet http:///
page 53 of 54 instruction group mnemonic usage opeation s cy 59 data transfer lpg lpg #n1 pg = #n1 s 60 lra lra r [r] a s 61 lar lar r a [r] s 62 lri lri r,#n4 [r] = #n4 s 63 increment inc inc abr abr++ - 64 branch br br !abs if s bit of sfr = 1, absolute branch, pc !abs s 65 br @abr if s bit of sfr = 1, indirect branch, pg+pc abr s 66 subroutine call call !abs if s bit of sfr = 1, ads pg+pc, sp sp - 1, pc !abs s 67 call @abr if s bit of sfr = 1, ads pg+pc, sp sp - 1, pg+pc abr s 68 ret ret sp sp+1, pg+pc ads s 69 reti reti spsfr spsfr+1, sfr m(spsfr) sp sp+1, pg+pc ads s 70 etc nop nop s 71 stop stop s 72 wdtc wdtc watch dog timer clear s 73 spc spc stack pointer clear s 74 xor xor m(dp) a = a m(dp) a = a m(dp+x+y) at d flag of sfr is set. s 75 eix eix index bit of sfr is set. s 76 dix dix index bit of sfr is clear. s 77 ei ei interrupt bit of sfr is set. s 78 di di interrupt bit of sfr is clear. s 79 cmpl cmpl a = a + 1 z **[note] the instruction ldw @abr execution time is 2cycle and execution process is as follow. sp = sp - 1 , ads ? pg+pc , pg+pc ? abr , dbr ? (pg+pc) , pg+pc ? ads , sp = sp+1 ** carry bit(cy) hold previous value before execution clrc/setc instruction . symbols have meaning as follows. o : carry bit is only set when overflow has occurred in operation. w : carry bit is only set when borrow has occurred in operation. r : carry bit is only set or reset according to shift bit. ** status bit(s) indicates conditions for changing status. symbols have meaning as follows. s : on executing an instruction, status bit is unconditionally set. c : status bit is only set when overflow has occurred in operation. b : status bit is only set when underflow has not occurred in operation. e : status bit is only set when equality is found in comparison. n : status bit is only set when equality is not found in comparison. z : status bit only set when the result is zero. t : status bit only set when the carry has occurred in operation + + 11. instruction set adam41p272x free datasheet http:///
page 54 of 54 12. ordering information 12. ordering information 13. development system in - circuit emulator adam4 ice assembler adam assembler mtp writer (gang4) adam mtp programer fig 13.1 adam4 ice emulator fig 13.2 adam mtp programer C gang4 theadam41p272x are supported by in - circuit emulators , assembler and 4 - gang mtp programmer. adam41p272x rom size oscillator type ir led drive tr. pkg type ordering device 48k bytes (mtp) internal rc oscillator including ir led drive tr. 20 sop (300mil) ADAM41P2721 24 sop (300mil) adam41p2723 28 sop (300mil) adam41p2727 28 tssop (4.4mm) adam41p2727t excluding ir led drive tr. 20 sop (300mil) adam41p2720 24 sop (300mil) adam41p2724 28 sop (300mil) adam41p2728 28 tssop (4.4mm) adam41p2728t free datasheet http:///

▲Up To Search▲

Price & Availability of ADAM41P2721

	To Download ADAM41P2721 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .